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Memory Circuit Design Engineer / Leads (4 ~ 12 Yrs)

Location: Bangalore
Education: ME / MS / MTech, B.E/BTech in CSE/ IT/ ECE / EE
No. of Positions: 2
Business Group:
Industry: Semiconductor Jobs
Posted date: 18th Nov 2011
Approx Hiring time in weeks: 30

Target Project/Product Details

Company Profile

Our client is based in Bangalore, the lab works on some of the leading edge technologies in the areas of Semiconductor Research (Compact & MultiScale Modeling, Nanotechnology, Lithography, Characterization), Technology Development (ASICs, Processors, IP Development, EDA, Test Tool Development), Systems SW (Operating Systems - AIX, Linux, zOS- Device Drivers), System Solutions (Hosted Client Solutions and SMB in a box), System Assurance and LAB Services, High Performance Computing, Performance Engineering

 They are the world's premier semiconductor design and systems development organization and has sustained its technology leadership position over the years. Our client delivers value to its clients with its technology innovation and expertise throughout the stack - from material sciences, processors, servers, storage and operating systems. These enable our client to integrate solutions for our clients around the world.

Skills

Key Skills:DRAM, SRAM, or even Flash circuit design
Must have Skills:DRAM, SRAM, or even Flash circuit design
Good to have Skills:Good Communication and leadership experience

Roles and Responsibilities

~ The individual will work closely with technologists worldwide to design circuits for validating embedded memory technologies in bleeding-edge process nodes.

~ The ideal candidate would have 4 ~ 8+ years of hands-on technical leadership in global semiconductor companies, with an emphasis on mixed-signal memory circuit design (could be DRAM, SRAM, or even Flash).

~ The candidate would have in-depth transistor level mastery of memory sense amplifiers and word/bit-line circuits such as line drivers, charge pumps, and DLL's.

~ The candidate would also have significant exposure to memory testing across various read/write modes, both at the probe and BIST levels.

~ The candidate would have a sustained record of leading ( for 8+ yrs ) small design teams with complete design ownership upto pad-cage/ESD level, including schematic, SPICE-level verification, layout, DRC/LVS/PEX/DFM, and tapeout.

~ The candidate would be very effective at global communication, manage global level projects, and be able to mentor junior engineers.

~ Plenty of scope for innovation and technical vitality

Contact Details

Company Name:World's Leading Semiconductor Research Labs @ Bangalore
Contact Email: dana@handigital.com